A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

Blog Article

This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency.Unlike the typical type-II single-loop PLL using a tri-state phase-frequency detector (PFD) plus a charge new belial model pump (CP) that has several limits in high-speed operation, our proposed PLL features a dual-loop scheme to enhance its performance and operating speed at low power.Specifically, we propose a dynamic frequency detector (FD) and a phase detector (PD) in conjunction with voltage-to-current converters (VICs) to avoid weboost splitter the typical current-mode-logic (CML) circuitry for static power reduction.Prototyped in 65-nm CMOS process, the entire PLL dissipates 10.

6 mW, of which the dynamic FD and PD merely consume 0.28 mW.The integrated jitter is 415.6 fsrms (10 kHz to 100 MHz) and the reference spur level is -53 dBc at a 26.

4-GHz output.